As a non-volatile memory capable of performing electrical writing and erasing, an electrically erasable and programmable read only memory (EEPROM) is widely used. A storage device represented by a flash memory and widely used in these days includes a conductive floating gate electrode or a trap insulation film surrounded by an oxide film below a gate electrode of a MISFET, and a charge accumulation state in the floating gate electrode or the trap insulation film are deemed as stored information and read as a threshold value of a transistor. This trap insulation film is an insulation film capable of accumulating a charge, and an example trap insulation film is a silicon nitride film. A threshold value of the MISFET is shifted by injecting/discharging a charge to/from such a charge accumulation region, and the MISFET is made to function as a storage element. An example flash memory described above is a split gate cell using a metal oxide nitride oxide semiconductor (MONOS) film. Such a memory has advantages that, since a charge is discretely accumulated through use of the silicon nitride film as the charge accumulation region, reliability of data retention is excellent compared to a conductive floating gate film, and since the reliability of data retention is excellent, the oxide films under and over the silicon nitride film can be thinned, and writing/erasing operation can be performed with low voltage.
Moreover, the split gate memory cell includes: a control gate electrode (selection gate electrode) formed over a semiconductor substrate via a first gate insulation film; and a memory gate electrode formed over the semiconductor substrate via a second gate insulation film including a charge accumulation region. Furthermore, the split gate memory cell includes a pair of semiconductor regions (a source region and a drain region) formed in a front surface of the semiconductor substrate so as to interpose the control gate electrode and the memory gate electrode, and the charge accumulation region is provided in the second gate insulation film.
Furthermore, Japanese Patent Application Laid-Open Publication No. 2006-41354 (Patent Document 1) discloses a split gate memory cell in which an active region in a protruding shape is formed on a front surface of the semiconductor substrate, and a control gate electrode and a memory gate electrode are arranged so as to straddle this protruding active region. Additionally, data writing is performed by the source side injection (SSI) writing method in which hot electrons generated in the semiconductor substrate are injected into a charge accumulation region, and data erasing is performed by the hot hole (band-to-band tunneling: BTBT) erasing method in which holes generated in the semiconductor substrate due to the band-to-band tunnel phenomenon are injected into the charge accumulation region.